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TDL for Parallel Processing
When multiplies and additions can be performed in parallel, the
computational complexity of a tapped delay line is
multiplies and
additions, where
is the number of
taps. This computational complexity is achieved by arranging the
additions into a binary tree, as shown in Fig.2.21 for the
case
.
Figure 2.21:
An example Tapped Delay Line (TDL),
with additions organized into a binary tree for maximized
parallel computation.

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