Further variations arise from analyzing the two-variable scattering
junction algebraically. In the case of two arbitrary real, positive,
scalar, waveguide impedances, the scattering relations are

The two-port normalized scattering matrix can be expressed as

where

The matrix is a (negated) Householder reflection, and it reflects any input across the line defined by the eigenvector . The quantities involved in (82) can be set to be and . The signal-flow graph obtained from (84) is the well-known normalized ladder section. The application of (82) in the two-port case leads to the signal-flow graph of Fig. 9.

It is worth noting that the realization of Fig. 9 can be implemented, for , with all coefficients in , thereby needing only a one-bit integer part. Parametrizing in terms of the reflection coefficient can be used to confine all parameters to the range , requiring no integer part. Note also that the junction computation consists of three sequential multiply-adds, as naturally fits the architecture of many current DSP chips.

The normalized 2-port junction can also be obtained by applying transformer coupling to a 2-multiply, 3-add unnormalized junction.

Consider the unnormalized section in Kelly-Lochbaum
form. Defining
, we can
write the outgoing pressure wave on the left port as

(84) |

For the right outgoing pressure wave we have

(85) |

With these algebraic manipulations we have obtained the 2-multiply 3-add unnormalized junction. It does not offer any benefit over the classic lattice or ladder sections; however, now consider normalization via transformer coupling. Figure 10 shows how to obtain the 3-multiply-add junction of Fig. 9: after transformer coupling the 2-multiply junction, just push the transformer into the junction and consolidate the multipliers.

So far, we have obtained three alternative realizations of the three-multiply, three-add, normalized junction. By comparing Figures 7, 8 and 9, we can say that, for an implementation on a general purpose DSP chip with a parallel multiply-add instruction, the junction of Fig. 9 seems to offer some benefit over the other two. In fact, we can organize the computations into three multiply-adds in series, thus achieving a better pipeline. For VLSI design, the direct implementation of the matrix product using the matrix (84) may be best, since it can be done with four parallel multiplications or CORDIC sections [38].

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