Go to the source code of this file.
Defines | |
| #define | __IOM161 1 |
| #define | AVR_MEGA 1 |
| #define | AVR_ENHANCED 1 |
| #define | UBRR1 0x00 |
| #define | UCSR1B 0x01 |
| #define | UCSR1A 0x02 |
| #define | UDR1 0x03 |
| #define | PINE 0x05 |
| #define | DDRE 0x06 |
| #define | PORTE 0x07 |
| #define | ACSR 0x08 |
| #define | UBRR0 0x09 |
| #define | UCSR0B 0x0A |
| #define | UCSR0A 0x0B |
| #define | UDR0 0x0C |
| #define | SPCR 0x0D |
| #define | SPSR 0x0E |
| #define | SPDR 0x0F |
| #define | PIND 0x10 |
| #define | DDRD 0x11 |
| #define | PORTD 0x12 |
| #define | PINC 0x13 |
| #define | DDRC 0x14 |
| #define | PORTC 0x15 |
| #define | PINB 0x16 |
| #define | DDRB 0x17 |
| #define | PORTB 0x18 |
| #define | PINA 0x19 |
| #define | DDRA 0x1A |
| #define | PORTA 0x1B |
| #define | EECR 0x1C |
| #define | EEDR 0x1D |
| #define | EEARL 0x1E |
| #define | EEARH 0x1F |
| #define | UBRRH 0x20 |
| #define | WDTCR 0x21 |
| #define | OCR2 0x22 |
| #define | TCNT2 0x23 |
| #define | ICR1L 0x24 |
| #define | ICR1H 0x25 |
| #define | ASSR 0x26 |
| #define | TCCR2 0x27 |
| #define | OCR1BL 0x28 |
| #define | OCR1BH 0x29 |
| #define | OCR1AL 0x2A |
| #define | OCR1AH 0x2B |
| #define | TCNT1L 0x2C |
| #define | TCNT1H 0x2D |
| #define | TCCR1B 0x2E |
| #define | TCCR1A 0x2F |
| #define | SFIOR 0x30 |
| #define | OCR0 0x31 |
| #define | TCNT0 0x32 |
| #define | TCCR0 0x33 |
| #define | MCUSR 0x34 |
| #define | MCUCR 0x35 |
| #define | EMCUCR 0x36 |
| #define | SPMCR 0x37 |
| #define | TIFR 0x38 |
| #define | TIMSK 0x39 |
| #define | GIFR 0x3A |
| #define | GIMSK 0x3B |
| #define | SPL 0x3D |
| #define | SPH 0x3E |
| #define | SREG 0x3F |
| #define | RESET_vect (0x00) |
| #define | INT0_vect (0x04) |
| #define | INT1_vect (0x08) |
| #define | INT2_vect (0x0C) |
| #define | TIMER2_COMP_vect (0x10) |
| #define | TIMER2_OVF_vect (0x14) |
| #define | TIMER1_CAPT_vect (0x18) |
| #define | TIMER1_COMPA_vect (0x1C) |
| #define | TIMER1_COMPB_vect (0x20) |
| #define | TIMER1_OVF_vect (0x24) |
| #define | TIMER0_COMP_vect (0x28) |
| #define | TIMER0_OVF_vect (0x2C) |
| #define | SPI_STC_vect (0x30) |
| #define | UART_RX_vect (0x34) |
| #define | UART1_RX_vect (0x38) |
| #define | UART_UDRE_vect (0x3C) |
| #define | UART1_UDRE_vect (0x40) |
| #define | UART_TX_vect (0x44) |
| #define | UART1_TX_vect (0x48) |
| #define | EE_RDY_vect (0x4C) |
| #define | ANA_COMP_vect (0x50) |
| #define | INT_VECT_SIZE (0x54) |
| #define | INT1 7 |
| #define | INT0 6 |
| #define | INT2 5 |
| #define | INTF1 7 |
| #define | INTF0 6 |
| #define | INTF2 5 |
| #define | TOIE1 7 |
| #define | OCIE1A 6 |
| #define | OCIE1B 5 |
| #define | TOIE2 4 |
| #define | TICIE1 3 |
| #define | OCIE2 2 |
| #define | TOIE0 1 |
| #define | OCIE0 0 |
| #define | TOV1 7 |
| #define | OCF1A 6 |
| #define | OCF1B 5 |
| #define | TOV2 4 |
| #define | ICF1 3 |
| #define | OCF2 2 |
| #define | TOV0 1 |
| #define | OCF0 0 |
| #define | SRE 7 |
| #define | SRW10 6 |
| #define | SE 5 |
| #define | SM1 4 |
| #define | ISC11 3 |
| #define | ISC10 2 |
| #define | ISC01 1 |
| #define | ISC00 0 |
| #define | SM0 7 |
| #define | SRL2 6 |
| #define | SRL1 5 |
| #define | SRL0 4 |
| #define | SRW01 3 |
| #define | SRW00 2 |
| #define | SRW11 1 |
| #define | ISC2 0 |
| #define | PSR2 1 |
| #define | PSR10 0 |
| #define | FOC0 7 |
| #define | PWM0 6 |
| #define | COM01 5 |
| #define | COM00 4 |
| #define | CTC0 3 |
| #define | CS02 2 |
| #define | CS01 1 |
| #define | CS00 0 |
| #define | FOC2 7 |
| #define | PWM2 6 |
| #define | COM21 5 |
| #define | COM20 4 |
| #define | CTC2 3 |
| #define | CS22 2 |
| #define | CS21 1 |
| #define | CS20 0 |
| #define | AS2 3 |
| #define | TCN2UB 2 |
| #define | OCR2UB 1 |
| #define | TCR2UB 0 |
| #define | COM1A1 7 |
| #define | COM1A0 6 |
| #define | COM1B1 5 |
| #define | COM1B0 4 |
| #define | FOC1A 3 |
| #define | FOC1B 2 |
| #define | PWM11 1 |
| #define | PWM10 0 |
| #define | ICNC1 7 |
| #define | ICES1 6 |
| #define | CTC1 3 |
| #define | CS12 2 |
| #define | CS11 1 |
| #define | CS10 0 |
| #define | WDTOE 4 |
| #define | WDE 3 |
| #define | WDP2 2 |
| #define | WDP1 1 |
| #define | WDP0 0 |
| #define | EERIE 3 |
| #define | EEMWE 2 |
| #define | EEWE 1 |
| #define | EERE 0 |
| #define | PA7 7 |
| #define | PA6 6 |
| #define | PA5 5 |
| #define | PA4 4 |
| #define | PA3 3 |
| #define | PA2 2 |
| #define | PA1 1 |
| #define | PA0 0 |
| #define | DDA7 7 |
| #define | DDA6 6 |
| #define | DDA5 5 |
| #define | DDA4 4 |
| #define | DDA3 3 |
| #define | DDA2 2 |
| #define | DDA1 1 |
| #define | DDA0 0 |
| #define | PINA7 7 |
| #define | PINA6 6 |
| #define | PINA5 5 |
| #define | PINA4 4 |
| #define | PINA3 3 |
| #define | PINA2 2 |
| #define | PINA1 1 |
| #define | PINA0 0 |
| #define | PB7 7 |
| #define | PB6 6 |
| #define | PB5 5 |
| #define | PB4 4 |
| #define | PB3 3 |
| #define | PB2 2 |
| #define | PB1 1 |
| #define | PB0 0 |
| #define | DDB7 7 |
| #define | DDB6 6 |
| #define | DDB5 5 |
| #define | DDB4 4 |
| #define | DDB3 3 |
| #define | DDB2 2 |
| #define | DDB1 1 |
| #define | DDB0 0 |
| #define | PINB7 7 |
| #define | PINB6 6 |
| #define | PINB5 5 |
| #define | PINB4 4 |
| #define | PINB3 3 |
| #define | PINB2 2 |
| #define | PINB1 1 |
| #define | PINB0 0 |
| #define | PC7 7 |
| #define | PC6 6 |
| #define | PC5 5 |
| #define | PC4 4 |
| #define | PC3 3 |
| #define | PC2 2 |
| #define | PC1 1 |
| #define | PC0 0 |
| #define | DDC7 7 |
| #define | DDC6 6 |
| #define | DDC5 5 |
| #define | DDC4 4 |
| #define | DDC3 3 |
| #define | DDC2 2 |
| #define | DDC1 1 |
| #define | DDC0 0 |
| #define | PINC7 7 |
| #define | PINC6 6 |
| #define | PINC5 5 |
| #define | PINC4 4 |
| #define | PINC3 3 |
| #define | PINC2 2 |
| #define | PINC1 1 |
| #define | PINC0 0 |
| #define | PD7 7 |
| #define | PD6 6 |
| #define | PD5 5 |
| #define | PD4 4 |
| #define | PD3 3 |
| #define | PD2 2 |
| #define | PD1 1 |
| #define | PD0 0 |
| #define | DDD7 7 |
| #define | DDD6 6 |
| #define | DDD5 5 |
| #define | DDD4 4 |
| #define | DDD3 3 |
| #define | DDD2 2 |
| #define | DDD1 1 |
| #define | DDD0 0 |
| #define | PIND7 7 |
| #define | PIND6 6 |
| #define | PIND5 5 |
| #define | PIND4 4 |
| #define | PIND3 3 |
| #define | PIND2 2 |
| #define | PIND1 1 |
| #define | PIND0 0 |
| #define | PE2 2 |
| #define | PE1 1 |
| #define | PE0 0 |
| #define | DDE2 2 |
| #define | DDE1 1 |
| #define | DDE0 0 |
| #define | PINE2 2 |
| #define | PINE1 1 |
| #define | PINE0 0 |
| #define | SPIF 7 |
| #define | WCOL 6 |
| #define | SPI2X 0 |
| #define | SPIE 7 |
| #define | SPE 6 |
| #define | DORD 5 |
| #define | MSTR 4 |
| #define | CPOL 3 |
| #define | CPHA 2 |
| #define | SPR1 1 |
| #define | SPR0 0 |
| #define | RXC0 7 |
| #define | TXC0 6 |
| #define | UDRE0 5 |
| #define | FE0 4 |
| #define | OVR0 3 |
| #define | U2X0 1 |
| #define | MPCM0 0 |
| #define | RXC1 7 |
| #define | TXC1 6 |
| #define | UDRE1 5 |
| #define | FE1 4 |
| #define | OVR1 3 |
| #define | U2X1 1 |
| #define | MPCM1 0 |
| #define | RXCIE0 7 |
| #define | TXCIE0 6 |
| #define | UDRIE0 5 |
| #define | RXEN0 4 |
| #define | TXEN0 3 |
| #define | CHR90 2 |
| #define | RXB80 1 |
| #define | TXB80 0 |
| #define | RXCIE1 7 |
| #define | TXCIE1 6 |
| #define | UDRIE1 5 |
| #define | RXEN1 4 |
| #define | TXEN1 3 |
| #define | CHR91 2 |
| #define | RXB81 1 |
| #define | TXB81 0 |
| #define | ACD 7 |
| #define | AINBG 6 |
| #define | ACO 5 |
| #define | ACI 4 |
| #define | ACIE 3 |
| #define | ACIC 2 |
| #define | ACIS1 1 |
| #define | ACIS0 0 |
| #define | XL r26 |
| #define | XH r27 |
| #define | YL r28 |
| #define | YH r29 |
| #define | ZL r30 |
| #define | ZH r31 |
| #define | RAMEND 0x45F |
| #define | XRAMEND 0xFFFF |
| #define | E2END 0x1FF |
| #define | FLASHEND 0x3FFF |
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1.2.8.1 written by Dimitri van Heesch,
© 1997-2001