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Defines | |
#define | __IOTN11 1 |
#define | ACSR 0x08 |
#define | PINB 0x16 |
#define | DDRB 0x17 |
#define | PORTB 0x18 |
#define | WDTCR 0x21 |
#define | TCNT0 0x32 |
#define | TCCR0 0x33 |
#define | MCUSR 0x34 |
#define | MCUCR 0x35 |
#define | TIFR 0x38 |
#define | TIMSK 0x39 |
#define | GIFR 0x3A |
#define | GIMSK 0x3B |
#define | SREG 0x3F |
#define | RESET_vect (0x00) |
#define | INT0_vect (0x02) |
#define | PIN_vect (0x04) |
#define | TIMER0_OVF_vect (0x06) |
#define | ANA_COMP_vect (0x08) |
#define | INT_VECT_SIZE (0x0A) |
#define | INT0 6 |
#define | PCIE 5 |
#define | INTF0 6 |
#define | PCIF 5 |
#define | TOIE0 1 |
#define | TOV0 1 |
#define | SE 5 |
#define | SM 4 |
#define | ISC01 1 |
#define | ISC00 0 |
#define | CS02 2 |
#define | CS01 1 |
#define | CS00 0 |
#define | WDTOE 4 |
#define | WDE 3 |
#define | WDP2 2 |
#define | WDP1 1 |
#define | WDP0 0 |
#define | PB4 4 |
#define | PB3 3 |
#define | PB2 2 |
#define | PB1 1 |
#define | PB0 0 |
#define | DDB4 4 |
#define | DDB3 3 |
#define | DDB2 2 |
#define | DDB1 1 |
#define | DDB0 0 |
#define | PINB5 5 |
#define | PINB4 4 |
#define | PINB3 3 |
#define | PINB2 2 |
#define | PINB1 1 |
#define | PINB0 0 |
#define | ACD 7 |
#define | ACO 5 |
#define | ACI 4 |
#define | ACIE 3 |
#define | ACIS1 1 |
#define | ACIS0 0 |
#define | ZL r30 |
#define | ZH r31 |
#define | RAMEND 0x1F |
#define | XRAMEND 0x0 |
#define | E2END 0x0 |
#define | FLASHEND 0x3FF |
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