Go to the source code of this file.
Defines | |
| #define | __IO2333 1 |
| #define | UBRRH 0x03 |
| #define | ADCL 0x04 |
| #define | ADCH 0x05 |
| #define | ADCSR 0x06 |
| #define | ADMUX 0x07 |
| #define | ACSR 0x08 |
| #define | UBRR 0x09 |
| #define | UBRRL 0x09 |
| #define | UCSRB 0x0A |
| #define | UCSRA 0x0B |
| #define | UDR 0x0C |
| #define | SPCR 0x0D |
| #define | SPSR 0x0E |
| #define | SPDR 0x0F |
| #define | PIND 0x10 |
| #define | DDRD 0x11 |
| #define | PORTD 0x12 |
| #define | PINC 0x13 |
| #define | DDRC 0x14 |
| #define | PORTC 0x15 |
| #define | PINB 0x16 |
| #define | DDRB 0x17 |
| #define | PORTB 0x18 |
| #define | EECR 0x1C |
| #define | EEDR 0x1D |
| #define | EEARL 0x1E |
| #define | WDTCR 0x21 |
| #define | ICR1L 0x26 |
| #define | ICR1H 0x27 |
| #define | OCR1L 0x2A |
| #define | OCR1H 0x2B |
| #define | TCNT1L 0x2C |
| #define | TCNT1H 0x2D |
| #define | TCCR1B 0x2E |
| #define | TCCR1A 0x2F |
| #define | TCNT0 0x32 |
| #define | TCCR0 0x33 |
| #define | MCUSR 0x34 |
| #define | MCUCR 0x35 |
| #define | TIFR 0x38 |
| #define | TIMSK 0x39 |
| #define | GIFR 0x3A |
| #define | GIMSK 0x3B |
| #define | SPL 0x3D |
| #define | SPH 0x3E |
| #define | SREG 0x3F |
| #define | RESET_vect (0x00) |
| #define | INT0_vect (0x02) |
| #define | INT1_vect (0x04) |
| #define | TIMER1_CAPT_vect (0x06) |
| #define | TIMER1_COMPA_vect (0x08) |
| #define | TIMER1_OVF_vect (0x0A) |
| #define | TIMER0_OVF_vect (0x0C) |
| #define | SPI_STC_vect (0x0E) |
| #define | UART_RX_vect (0x10) |
| #define | UART_UDRE_vect (0x12) |
| #define | UART_TX_vect (0x14) |
| #define | ADC_vect (0x16) |
| #define | EE_RDY_vect (0x18) |
| #define | ANA_COMP_vect (0x1A) |
| #define | INT_VECT_SIZE (0x1C) |
| #define | WDRF 3 |
| #define | BORF 2 |
| #define | EXTRF 1 |
| #define | PORF 0 |
| #define | INT1 7 |
| #define | INT0 6 |
| #define | INTF1 7 |
| #define | INTF0 6 |
| #define | TOIE1 7 |
| #define | OCIE1 6 |
| #define | TICIE1 3 |
| #define | TOIE0 1 |
| #define | TOV1 7 |
| #define | OCF1 6 |
| #define | ICF1 3 |
| #define | TOV0 1 |
| #define | SE 5 |
| #define | SM 4 |
| #define | ISC11 3 |
| #define | ISC10 2 |
| #define | ISC01 1 |
| #define | ISC00 0 |
| #define | CS02 2 |
| #define | CS01 1 |
| #define | CS00 0 |
| #define | COM11 7 |
| #define | COM10 6 |
| #define | PWM11 1 |
| #define | PWM10 0 |
| #define | ICNC1 7 |
| #define | ICES1 6 |
| #define | CTC1 3 |
| #define | CS12 2 |
| #define | CS11 1 |
| #define | CS10 0 |
| #define | WDTOE 4 |
| #define | WDE 3 |
| #define | WDP2 2 |
| #define | WDP1 1 |
| #define | WDP0 0 |
| #define | EERIE 3 |
| #define | EEMWE 2 |
| #define | EEWE 1 |
| #define | EERE 0 |
| #define | SPIE 7 |
| #define | SPE 6 |
| #define | DORD 5 |
| #define | MSTR 4 |
| #define | CPOL 3 |
| #define | CPHA 2 |
| #define | SPR1 1 |
| #define | SPR0 0 |
| #define | SPIF 7 |
| #define | WCOL 6 |
| #define | RXC 7 |
| #define | TXC 6 |
| #define | UDRE 5 |
| #define | FE 4 |
| #define | OVR 3 |
| #define | MPCM 0 |
| #define | RXCIE 7 |
| #define | TXCIE 6 |
| #define | UDRIE 5 |
| #define | RXEN 4 |
| #define | TXEN 3 |
| #define | CHR9 2 |
| #define | RXB8 1 |
| #define | TXB8 0 |
| #define | ACD 7 |
| #define | AINBG 6 |
| #define | ACO 5 |
| #define | ACI 4 |
| #define | ACIE 3 |
| #define | ACIC 2 |
| #define | ACIS1 1 |
| #define | ACIS0 0 |
| #define | ACDBG 6 |
| #define | MUX2 2 |
| #define | MUX1 1 |
| #define | MUX0 0 |
| #define | ADEN 7 |
| #define | ADSC 6 |
| #define | ADFR 5 |
| #define | ADIF 4 |
| #define | ADIE 3 |
| #define | ADPS2 2 |
| #define | ADPS1 1 |
| #define | ADPS0 0 |
| #define | PB5 5 |
| #define | PB4 4 |
| #define | PB3 3 |
| #define | PB2 2 |
| #define | PB1 1 |
| #define | PB0 0 |
| #define | DDB5 5 |
| #define | DDB4 4 |
| #define | DDB3 3 |
| #define | DDB2 2 |
| #define | DDB1 1 |
| #define | DDB0 0 |
| #define | PINB5 5 |
| #define | PINB4 4 |
| #define | PINB3 3 |
| #define | PINB2 2 |
| #define | PINB1 1 |
| #define | PINB0 0 |
| #define | PC5 5 |
| #define | PC4 4 |
| #define | PC3 3 |
| #define | PC2 2 |
| #define | PC1 1 |
| #define | PC0 0 |
| #define | DDC5 5 |
| #define | DDC4 4 |
| #define | DDC3 3 |
| #define | DDC2 2 |
| #define | DDC1 1 |
| #define | DDC0 0 |
| #define | PINC5 5 |
| #define | PINC4 4 |
| #define | PINC3 3 |
| #define | PINC2 2 |
| #define | PINC1 1 |
| #define | PINC0 0 |
| #define | PD7 7 |
| #define | PD6 6 |
| #define | PD5 5 |
| #define | PD4 4 |
| #define | PD3 3 |
| #define | PD2 2 |
| #define | PD1 1 |
| #define | PD0 0 |
| #define | DDD7 7 |
| #define | DDD6 6 |
| #define | DDD5 5 |
| #define | DDD4 4 |
| #define | DDD3 3 |
| #define | DDD2 2 |
| #define | DDD1 1 |
| #define | DDD0 0 |
| #define | PIND7 7 |
| #define | PIND6 6 |
| #define | PIND5 5 |
| #define | PIND4 4 |
| #define | PIND3 3 |
| #define | PIND2 2 |
| #define | PIND1 1 |
| #define | PIND0 0 |
| #define | XL r26 |
| #define | XH r27 |
| #define | YL r28 |
| #define | YH r29 |
| #define | ZL r30 |
| #define | ZH r31 |
| #define | RAMEND 0xDF |
| #define | XRAMEND 0xDF |
| #define | E2END 0x7F |
| #define | FLASHEND 0x7FF |
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1.2.8.1 written by Dimitri van Heesch,
© 1997-2001