Go to the source code of this file.
Defines | |
| #define | __IOTN15 1 |
| #define | ADCL 0x04 |
| #define | ADCH 0x05 |
| #define | ADCSR 0x06 |
| #define | ADMUX 0x07 |
| #define | ACSR 0x08 |
| #define | PINB 0x16 |
| #define | DDRB 0x17 |
| #define | PORTB 0x18 |
| #define | EECR 0x1C |
| #define | EEDR 0x1D |
| #define | EEARL 0x1E |
| #define | WDTCR 0x21 |
| #define | SFIOR 0x2C |
| #define | OCR1B 0x2D |
| #define | OCR1A 0x2E |
| #define | TCNT1 0x2F |
| #define | TCCR1 0x30 |
| #define | OSCCAL 0x31 |
| #define | TCNT0 0x32 |
| #define | TCCR0 0x33 |
| #define | MCUSR 0x34 |
| #define | MCUCR 0x35 |
| #define | TIFR 0x38 |
| #define | TIMSK 0x39 |
| #define | GIFR 0x3A |
| #define | GIMSK 0x3B |
| #define | SREG 0x3F |
| #define | RESET_vect (0x00) |
| #define | INT0_vect (0x02) |
| #define | PIN_vect (0x04) |
| #define | TIMER1_COMPA_vect (0x06) |
| #define | TIMER1_OVF_vect (0x08) |
| #define | TIMER0_OVF_vect (0x0A) |
| #define | EE_RDY_vect (0x0C) |
| #define | ANA_COMP_vect (0x0E) |
| #define | ADC_vect (0x10) |
| #define | INT_VECT_SIZE (0x12) |
| #define | INT0 6 |
| #define | PCIE 5 |
| #define | INTF0 6 |
| #define | PCIF 5 |
| #define | OCIE1 6 |
| #define | TOIE1 2 |
| #define | TOIE0 1 |
| #define | OCF1 6 |
| #define | TOV1 2 |
| #define | TOV0 1 |
| #define | PUD 6 |
| #define | SE 5 |
| #define | SM1 4 |
| #define | SM0 3 |
| #define | ISC01 1 |
| #define | ISC00 0 |
| #define | WDRF 3 |
| #define | BORF 2 |
| #define | EXTRF 1 |
| #define | PORF 0 |
| #define | CS02 2 |
| #define | CS01 1 |
| #define | CS00 0 |
| #define | CTC1 7 |
| #define | PWM1 6 |
| #define | COM1A1 5 |
| #define | COM1A0 4 |
| #define | CS13 3 |
| #define | CS12 2 |
| #define | CS11 1 |
| #define | CS10 0 |
| #define | FOC1A 2 |
| #define | PSR1 1 |
| #define | PSR0 0 |
| #define | WDTOE 4 |
| #define | WDE 3 |
| #define | WDP2 2 |
| #define | WDP1 1 |
| #define | WDP0 0 |
| #define | EERIE 3 |
| #define | EEMWE 2 |
| #define | EEWE 1 |
| #define | EERE 0 |
| #define | PORTB4 4 |
| #define | PORTB3 3 |
| #define | PORTB2 2 |
| #define | PORTB1 1 |
| #define | PORTB0 0 |
| #define | DDB4 4 |
| #define | DDB3 3 |
| #define | DDB2 2 |
| #define | DDB1 1 |
| #define | DDB0 0 |
| #define | PINB5 5 |
| #define | PINB4 4 |
| #define | PINB3 3 |
| #define | PINB2 2 |
| #define | PINB1 1 |
| #define | PINB0 0 |
| #define | ACD 7 |
| #define | GREF 6 |
| #define | ACO 5 |
| #define | ACI 4 |
| #define | ACIE 3 |
| #define | ACIS1 1 |
| #define | ACIS0 0 |
| #define | REFS1 7 |
| #define | REFS0 6 |
| #define | ADLAR 5 |
| #define | MUX2 2 |
| #define | MUX1 1 |
| #define | MUX0 0 |
| #define | ADEN 7 |
| #define | ADSC 6 |
| #define | ADFR 5 |
| #define | ADIF 4 |
| #define | ADIE 3 |
| #define | ADPS2 2 |
| #define | ADPS1 1 |
| #define | ADPS0 0 |
| #define | ZL r30 |
| #define | ZH r31 |
| #define | RAMEND 0x1F |
| #define | XRAMEND 0x0 |
| #define | E2END 0x3F |
| #define | FLASHEND 0x3FF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.2.8.1 written by Dimitri van Heesch,
© 1997-2001