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Defines | |
#define | __IO76C711 1 |
#define | AVR_MEGA 1 |
#define | AVR_ENHANCED 1 |
#define | SPCR 0x0D |
#define | SPSR 0x0E |
#define | SPDR 0x0F |
#define | PIND 0x10 |
#define | DDRD 0x11 |
#define | PORTD 0x12 |
#define | PERIPHEN 0x13 |
#define | CLK_CNTR 0x14 |
#define | PORTC 0x15 |
#define | PINB 0x16 |
#define | DDRB 0x17 |
#define | PORTB 0x18 |
#define | PINA 0x19 |
#define | DDRA 0x1A |
#define | PORTA 0x1B |
#define | IRDAMOD 0x20 |
#define | WDTCR 0x21 |
#define | ICR1L 0x26 |
#define | ICR1H 0x27 |
#define | OCR1BL 0x28 |
#define | OCR1BH 0x29 |
#define | OCR1AL 0x2A |
#define | OCR1AH 0x2B |
#define | TCNT1L 0x2C |
#define | TCNT1H 0x2D |
#define | TCCR1B 0x2E |
#define | TCCR1A 0x2F |
#define | PRELD 0x31 |
#define | TCNT0 0x32 |
#define | TCCR0 0x33 |
#define | MCUSR 0x34 |
#define | MCUCR 0x35 |
#define | TIFR 0x36 |
#define | TIMSK 0x37 |
#define | EIMSK 0x39 |
#define | SPL 0x3D |
#define | SPH 0x3E |
#define | SREG 0x3F |
#define | RESET_vect (0x00) |
#define | SUSP_RESM_vect (0x04) |
#define | INT0_vect (0x08) |
#define | TIMER1_CAPT_vect (0x0C) |
#define | TIMER1_COMPA_vect (0x10) |
#define | TIMER1_COMPB_vect (0x14) |
#define | TIMER1_OVF_vect (0x18) |
#define | TIMER0_OVF_vect (0x1C) |
#define | SPI_STC_vect (0x20) |
#define | TDMAC_vect (0x24) |
#define | UART0_vect (0x28) |
#define | RDMAC_vect (0x2C) |
#define | USB_HW_vect (0x30) |
#define | UART1_vect (0x34) |
#define | INT1_vect (0x38) |
#define | INT_VECT_SIZE (0x3C) |
#define | POL1 3 |
#define | POL0 2 |
#define | INT1 1 |
#define | INT0 0 |
#define | TOIE1 7 |
#define | OCIE1A 6 |
#define | OCIE1B 5 |
#define | TICIE1 3 |
#define | TOIE0 1 |
#define | TOV1 7 |
#define | OCF1A 6 |
#define | OCF1B 5 |
#define | ICF1 3 |
#define | TOV0 1 |
#define | SE 5 |
#define | SM1 4 |
#define | SM0 3 |
#define | EXTRF 1 |
#define | PORF 0 |
#define | COM01 5 |
#define | COM00 4 |
#define | CTC0 3 |
#define | CS02 2 |
#define | CS01 1 |
#define | CS00 0 |
#define | COM1A1 7 |
#define | COM1A0 6 |
#define | COM1B1 5 |
#define | COM1B0 4 |
#define | ICNC1 7 |
#define | ICES1 6 |
#define | CTC1 3 |
#define | CS12 2 |
#define | CS11 1 |
#define | CS10 0 |
#define | WDTOE 4 |
#define | WDE 3 |
#define | WDP2 2 |
#define | WDP1 1 |
#define | WDP0 0 |
#define | POL 2 |
#define | MODE 1 |
#define | EN 0 |
#define | PA7 7 |
#define | PA6 6 |
#define | PA5 5 |
#define | PA4 4 |
#define | PA3 3 |
#define | PA2 2 |
#define | PA1 1 |
#define | PA0 0 |
#define | DDA7 7 |
#define | DDA6 6 |
#define | DDA5 5 |
#define | DDA4 4 |
#define | DDA3 3 |
#define | DDA2 2 |
#define | DDA1 1 |
#define | DDA0 0 |
#define | PINA7 7 |
#define | PINA6 6 |
#define | PINA5 5 |
#define | PINA4 4 |
#define | PINA3 3 |
#define | PINA2 2 |
#define | PINA1 1 |
#define | PINA0 0 |
#define | PB7 7 |
#define | PB6 6 |
#define | PB5 5 |
#define | PB4 4 |
#define | PB3 3 |
#define | PB2 2 |
#define | PB1 1 |
#define | PB0 0 |
#define | DDB7 7 |
#define | DDB6 6 |
#define | DDB5 5 |
#define | DDB4 4 |
#define | DDB3 3 |
#define | DDB2 2 |
#define | DDB1 1 |
#define | DDB0 0 |
#define | PINB7 7 |
#define | PINB6 6 |
#define | PINB5 5 |
#define | PINB4 4 |
#define | PINB3 3 |
#define | PINB2 2 |
#define | PINB1 1 |
#define | PINB0 0 |
#define | PC3 3 |
#define | PC2 2 |
#define | PC1 1 |
#define | PC0 0 |
#define | PD7 7 |
#define | PD6 6 |
#define | PD5 5 |
#define | PD4 4 |
#define | PD3 3 |
#define | PD2 2 |
#define | PD1 1 |
#define | PD0 0 |
#define | DDD7 7 |
#define | DDD6 6 |
#define | DDD5 5 |
#define | DDD4 4 |
#define | DDD3 3 |
#define | DDD2 2 |
#define | DDD1 1 |
#define | DDD0 0 |
#define | PIND7 7 |
#define | PIND6 6 |
#define | PIND5 5 |
#define | PIND4 4 |
#define | PIND3 3 |
#define | PIND2 2 |
#define | PIND1 1 |
#define | PIND0 0 |
#define | UOSC 4 |
#define | UCK 3 |
#define | IRCK 2 |
#define | IRDA 2 |
#define | UART 1 |
#define | USB 0 |
#define | SPIF 7 |
#define | WCOL 6 |
#define | SPIE 7 |
#define | SPE 6 |
#define | DORD 5 |
#define | MSTR 4 |
#define | CPOL 3 |
#define | CPHA 2 |
#define | SPR1 1 |
#define | SPR0 0 |
#define | UART0_BASE 0x2020 |
#define | UART1_BASE 0x2030 |
#define | US_RHR 0x00 |
#define | US_THR 0x00 |
#define | US_IER 0x01 |
#define | US_FCR 0x02 |
#define | US_PMR 0x03 |
#define | US_MR 0x04 |
#define | US_CSR 0x05 |
#define | US_CR 0x06 |
#define | US_BL 0x07 |
#define | US_BM 0x08 |
#define | US_RTO 0x09 |
#define | US_TTG 0x0A |
#define | DMA_BASE 0x2000 |
#define | TXTADL 0x01 |
#define | TXPLL 0x03 |
#define | TXPLM 0x04 |
#define | TXTPLL 0x05 |
#define | TXTPLM 0x06 |
#define | RXTADL 0x07 |
#define | RXTADMEN 0x08 |
#define | RSPLL 0x09 |
#define | RXPLM 0x0A |
#define | RXTPLL 0x0B |
#define | RXTPLM 0x0C |
#define | INTCST 0x0D |
#define | PROGRAM_MEMORY_CONTROL_BIT 0x2040 |
#define | USB_BASE 0x1000 |
#define | FRM_NUM_H 0x0FD |
#define | FRM_NUM_L 0x0FC |
#define | GLB_STATE 0x0FB |
#define | SPRSR 0x0FA |
#define | SPRSIE 0x0F9 |
#define | UISR 0x0F7 |
#define | UIAR 0x0F5 |
#define | FADDR 0x0F2 |
#define | ENDPPGPG 0x0F1 |
#define | ECR0 0x0EF |
#define | ECR1 0x0EE |
#define | ECR2 0x0ED |
#define | ECR3 0x0EC |
#define | ECR4 0x0EB |
#define | ECR5 0x0EA |
#define | ECR6 0x0E9 |
#define | ECR7 0x0E8 |
#define | CSR0 0x0DF |
#define | CSR1 0x0DE |
#define | CSR2 0x0DD |
#define | CSR3 0x0DC |
#define | CSR4 0x0DB |
#define | CSR5 0x0DA |
#define | CSR6 0x0D9 |
#define | CSR7 0x0D8 |
#define | FDR0 0x0CF |
#define | FDR1 0x0CE |
#define | FDR2 0x0CD |
#define | FDR3 0x0CC |
#define | FDR4 0x0CB |
#define | FDR5 0x0CA |
#define | FDR6 0x0C9 |
#define | FDR7 0x0C8 |
#define | FBYTE_CNT0_L 0x0BF |
#define | FBYTE_CNT1_L 0x0BE |
#define | FBYTE_CNT2_L 0x0BD |
#define | FBYTE_CNT3_L 0x0BC |
#define | FBYTE_CNT4_L 0x0BB |
#define | FBYTE_CNT5_L 0x0BA |
#define | FBYTE_CNT6_L 0x0B9 |
#define | FBYTE_CNT7_L 0x0B8 |
#define | FBYTE_CNT0_H 0x0AF |
#define | FBYTE_CNT1_H 0x0AE |
#define | FBYTE_CNT2_H 0x0AD |
#define | FBYTE_CNT3_H 0x0AC |
#define | FBYTE_CNT4_H 0x0AB |
#define | FBYTE_CNT5_H 0x0AA |
#define | FBYTE_CNT6_H 0x0A9 |
#define | FBYTE_CNT7_H 0x0A8 |
#define | SLP_MD_EN 0x100 |
#define | IRQ_EN 0x101 |
#define | IRQ_STAT 0x102 |
#define | SUSP_WUP 0x103 |
#define | PA_EN 0x104 |
#define | USB_DMA_ADL 0x105 |
#define | USB_DMA_ADH 0x106 |
#define | USB_DMA_PLR 0x107 |
#define | USB_DMA_EAD 0x108 |
#define | USB_DMA_PLT 0x109 |
#define | USB_DMA_EN 0x10A |
#define | XL r26 |
#define | XH r27 |
#define | YL r28 |
#define | YH r29 |
#define | ZL r30 |
#define | ZH r31 |
#define | RAMEND 0x07FF |
#define | XRAMEND 0x07FF |
#define | E2END 0 |
#define | FLASHEND 0x3FFF |
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