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Yet Another Three-Multiply Normalized Lattice.

Further variations arise from analyzing the two-variable scattering junction algebraically. In the case of two arbitrary real, positive, scalar, waveguide impedances, the scattering relations are

$\displaystyle \left[\begin{array}{l} p_1^- \\  p_2^- \end{array}\right]$ $\textstyle =$ $\displaystyle \left[
\displaystyle
\begin{array}{ll}
\frac{2 \Gamma_{1}}{\Gamma...
...\end{array} \right]
\left[\begin{array}{rr} p_1^+ \\  p_2^+ \end{array} \right]$  
  $\textstyle =$ $\displaystyle {\mbox{\boldmath$A$}}\left[
\begin{array}{rr} p_1^+ \\  p_2^+ \end{array} \right]$ (82)

The two-port normalized scattering matrix can be expressed as
\begin{displaymath}
{\tilde {\mbox{\boldmath$A$}}}=\left[
\begin{array}{rr}
\cos...
...ta}) \\
\sin({\theta}) & -\cos({\theta})
\end{array} \right]
\end{displaymath} (83)

where

\begin{displaymath}
\cos({\theta}) {\tiny\stackrel{\triangle}{=}}\frac{\Gamma_1-...
...ngle}{=}}\frac{2 \sqrt{\Gamma_1 \Gamma_2}}{\Gamma_1+\Gamma_2}.
\end{displaymath}

The matrix ${\tilde {\mbox{\boldmath$A$}}}$ is a (negated) Householder reflection, and it reflects any input across the line defined by the eigenvector $[\cos(\theta/2),\sin(\theta/2)]$. The quantities involved in (82) can be set to be ${\mbox{\boldmath$u$}}_n^T =\left[
\begin{array}{ll} 1 & g \end{array} \right] = \left[
\begin{array}{ll} 1 & \sqrt{\Gamma_2/\Gamma_1} \end{array} \right] $ and $\beta = \alpha_1 = 2\Gamma_1/(\Gamma_1
+ \Gamma_2)$. The signal-flow graph obtained from (84) is the well-known normalized ladder section. The application of (82) in the two-port case leads to the signal-flow graph of Fig. 9.

Figure 9: A three-multiply-add normalized junction.
\begin{figure}\centerline{\epsfbox{figure/Junc.eps}}\end{figure}

It is worth noting that the realization of Fig. 9 can be implemented, for $\Gamma_1>\Gamma_2$, with all coefficients in $\left[-2,
2\right)$, thereby needing only a one-bit integer part. Parametrizing in terms of the reflection coefficient $\rho = \alpha - 1$ can be used to confine all parameters to the range $[-1,1)$, requiring no integer part. Note also that the junction computation consists of three sequential multiply-adds, as naturally fits the architecture of many current DSP chips.

The normalized 2-port junction can also be obtained by applying transformer coupling to a 2-multiply, 3-add unnormalized junction.

Consider the unnormalized $2 \times 2$ section in Kelly-Lochbaum form. Defining $\rho=\frac{\Gamma_1-\Gamma_2}{\Gamma_1+\Gamma_2}$, we can write the outgoing pressure wave on the left port as

$\displaystyle {p_1^- }
= \rho p_1^+ + (1-\rho)p_2^+$
  $\textstyle =$ $\displaystyle \rho p_1^+ + p_1^+ - p_1^+ + \frac{1-\rho}{1+\rho} (1+\rho)p_2^+$  
  $\textstyle =$ $\displaystyle \beta p_1^+ - p_1^+ + \frac{\Gamma_2}{\Gamma_1}\beta p_2^+$  
  $\textstyle =$ $\displaystyle - p_1^+ + \beta (p_1^+ + \frac{\Gamma_2}{\Gamma_1} p_2^+)$ (84)

For the right outgoing pressure wave we have
$\displaystyle p_2^-$ $\textstyle =$ $\displaystyle (1+\rho) p_1^+ - \rho p_2^+$  
  $\textstyle =$ $\displaystyle \beta p_1^+ - \rho p_2^+ - p_2^+ + p_2^+$  
  $\textstyle =$ $\displaystyle \beta p_1^+ - p_2^+ + \frac{\Gamma_2}{\Gamma_1}\beta p_2^+$  
  $\textstyle =$ $\displaystyle - p_2^+ + \beta \left(p_1^+ + \frac{\Gamma_2}{\Gamma_1} p_2^+\right)$ (85)

With these algebraic manipulations we have obtained the 2-multiply 3-add unnormalized junction. It does not offer any benefit over the classic lattice or ladder sections; however, now consider normalization via transformer coupling. Figure 10 shows how to obtain the 3-multiply-add junction of Fig. 9: after transformer coupling the 2-multiply junction, just push the transformer into the junction and consolidate the multipliers.
Figure 10: Obtaining a three-multiply-add normalized junction via transformer coupling.
\begin{figure}\centerline{\epsfbox{figure/Junc1.eps}}\end{figure}

So far, we have obtained three alternative realizations of the three-multiply, three-add, normalized junction. By comparing Figures 7, 8 and 9, we can say that, for an implementation on a general purpose DSP chip with a parallel multiply-add instruction, the junction of Fig. 9 seems to offer some benefit over the other two. In fact, we can organize the computations into three multiply-adds in series, thus achieving a better pipeline. For VLSI design, the direct implementation of the matrix product using the matrix (84) may be best, since it can be done with four parallel multiplications or CORDIC sections [38].


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``Aspects of Digital Waveguide Networks for Acoustic Modeling Applications'', by Julius O. Smith III and Davide Rocchesso , December 19, 1997, Web published at http://ccrma.stanford.edu/~jos/wgj/.
Copyright © 2007-02-07 by Julius O. Smith III and Davide Rocchesso
Center for Computer Research in Music and Acoustics (CCRMA),   Stanford University
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