Main Page   Compound List   File List   Compound Members   File Members  

iom103.h

Go to the documentation of this file.
00001 /*            - iom103.h -
00002 
00003    This file #defines the internal register addresses for ATMEGA103.
00004 */
00005 
00006 #ifndef __IOM103
00007 #define __IOM103 1
00008 
00009 #define AVR_MEGA 1
00010 
00011 /*==========================*/
00012 /* Predefined SFR Addresses */
00013 /*==========================*/
00014  
00015 /* Input Pins, Port F */
00016 #define PINF      0x00
00017  
00018 /* Input Pins, Port E */
00019 #define PINE      0x01
00020  
00021 /* Data Direction Register, Port E */
00022 #define DDRE      0x02
00023  
00024 /* Data Register, Port E */
00025 #define PORTE     0x03
00026  
00027 /* ADC Low Byte */
00028 #define ADCL      0x04
00029 #define ADCH      0x05
00030  
00031 /* ADC Control and status register */
00032 #define ADCSR     0x06
00033  
00034 /* ADC Multiplexer select */
00035 #define ADMUX     0x07
00036  
00037 /* Analog Comparator Control and Status Register */
00038 #define ACSR      0x08
00039 
00040 /* UART Baud Rate Register */
00041 #define UBRR      0x09
00042  
00043 /* UART Control Register */
00044 #define UCR       0x0A
00045  
00046 /* UART Status Register */
00047 #define USR       0x0B
00048 
00049 /* UART I/O Data Register */
00050 #define UDR       0x0C
00051  
00052 /* SPI Control Register */
00053 #define SPCR      0x0D
00054  
00055 /* SPI Status Register */
00056 #define SPSR      0x0E
00057  
00058 /* SPI I/O Data Register */
00059 #define SPDR      0x0F
00060  
00061 /* Input Pins, Port D */
00062 #define PIND      0x10
00063                                           
00064 /* Data Direction Register, Port D */
00065 #define DDRD      0x11
00066  
00067 /* Data Register, Port D */
00068 #define PORTD     0x12
00069  
00070 /* Data Register, Port C */
00071 #define PORTC     0x15
00072                       
00073 /* Input Pins, Port B */
00074 #define PINB      0x16
00075  
00076 /* Data Direction Register, Port B */
00077 #define DDRB      0x17
00078  
00079 /* Data Register, Port B */
00080 #define PORTB     0x18
00081   
00082 /* Input Pins, Port A */
00083 #define PINA      0x19
00084  
00085 /* Data Direction Register, Port A */
00086 #define DDRA      0x1A
00087  
00088 /* Data Register, Port A */
00089 #define PORTA     0x1B
00090   
00091 /* EEPROM Control Register */
00092 #define EECR      0x1C
00093 
00094 /* EEPROM Data Register */
00095 #define EEDR      0x1D
00096 
00097 /* EEPROM Address Register */
00098 #define EEARL     0x1E
00099 #define EEARH     0x1F
00100  
00101 /* Watchdog Timer Control Register */
00102 #define WDTCR     0x21
00103 
00104 /* Timer2 Output Compare Register */
00105 #define OCR2      0x23
00106 
00107 /* Timer/Counter 2 */
00108 #define TCNT2     0x24
00109  
00110 /* Timer/Counter 2 Control register */ 
00111 #define TCCR2     0x25
00112 
00113 /* T/C 1 Input Capture Register */
00114 #define ICR1L     0x26
00115 #define ICR1H     0x27
00116 
00117 /* Timer/Counter1 Output Compare Register B */ 
00118 #define OCR1BL    0x28
00119 #define OCR1BH    0x29
00120 
00121 /* Timer/Counter1 Output Compare Register A */
00122 #define OCR1AL    0x2A
00123 #define OCR1AH    0x2B
00124 
00125 /* Timer/Counter 1 */
00126 #define TCNT1L    0x2C
00127 #define TCNT1H    0x2D
00128  
00129 /* Timer/Counter 1 Control and Status Register */
00130 #define TCCR1B    0x2E
00131  
00132 /* Timer/Counter 1 Control Register */
00133 #define TCCR1A    0x2F
00134  
00135 /* Timer/Counter 0 Asynchronous Control & Status Register */
00136 #define ASSR      0x30
00137 
00138 /* Output Compare Register 0 */
00139 #define OCR0      0x31
00140 
00141 /* Timer/Counter 0 */
00142 #define TCNT0     0x32
00143  
00144 /* Timer/Counter 0 Control Register */
00145 #define TCCR0     0x33
00146 
00147 /* MCU Status Register */
00148 #define MCUSR     0x34
00149  
00150 /* MCU general Control Register */
00151 #define MCUCR     0x35
00152  
00153 /* Timer/Counter Interrupt Flag Register */
00154 #define TIFR      0x36
00155  
00156 /* Timer/Counter Interrupt MaSK register */
00157 #define TIMSK     0x37
00158  
00159 /* Èxternal Interrupt Flag Register */
00160 #define EIFR      0x38
00161  
00162 /* External Interrupt MaSK register */
00163 #define EIMSK      0x39
00164  
00165 /* External Interrupt Control Register */
00166 #define EICR      0x3A
00167 
00168 /* RAM Page Z select register */
00169 #define RAMPZ     0x3B
00170  
00171 /* XDIV Divide control register */
00172 #define XDIV      0x3C
00173 
00174 /* Stack Pointer */
00175 #define SPL      0x3D
00176 #define SPH      0x3E
00177 
00178 /* Status REGister */
00179 #define SREG      0x3F
00180 
00181 
00182 /*==============================*/
00183 /* Interrupt Vector Definitions */
00184 /*==============================*/
00185 
00186 /* NB! vectors are specified as byte addresses */
00187  
00188 #define    RESET_vect          (0x00)
00189 #define    INT0_vect           (0x04)
00190 #define    INT1_vect           (0x08)
00191 #define    INT2_vect           (0x0C)
00192 #define    INT3_vect           (0x10)
00193 #define    INT4_vect           (0x14)
00194 #define    INT5_vect           (0x18)
00195 #define    INT6_vect           (0x1C)
00196 #define    INT7_vect           (0x20)
00197 #define    TIMER2_COMP_vect    (0x24)
00198 #define    TIMER2_OVF_vect     (0x28)
00199 #define    TIMER1_CAPT_vect    (0x2C)
00200 #define    TIMER1_COMPA_vect   (0x30)
00201 #define    TIMER1_COMPB_vect   (0x34)
00202 #define    TIMER1_OVF_vect     (0x38)
00203 #define    TIMER0_COMP_vect    (0x3C)
00204 #define    TIMER0_OVF_vect     (0x40)
00205 #define    SPI_STC_vect        (0x44)
00206 #define    UART_RX_vect        (0x48)
00207 #define    UART_UDRE_vect      (0x4C)
00208 #define    UART_TX_vect        (0x50)
00209 #define    ADC_vect            (0x54)
00210 #define    EE_RDY_vect         (0x58)
00211 #define    ANA_COMP_vect       (0x5C)
00212 
00213 #define INT_VECT_SIZE (0x60)
00214 
00215 /*
00216    The Register Bit names are represented by their bit number (0-7).
00217 */                                                
00218 
00219 /* XDIV Divide control register*/
00220 #define    XDIVEN       7
00221 #define    XDIV6        6
00222 #define    XDIV5        5
00223 #define    XDIV4        4
00224 #define    XDIV3        3
00225 #define    XDIV2        2
00226 #define    XDIV1        1
00227 #define    XDIV0        0
00228  
00229 /* RAM Page Z select register */
00230 #define     RAMPZ0      0
00231  
00232 /* External Interrupt Control Register */ 
00233 #define    ISC71        7
00234 #define    ISC70        6
00235 #define    ISC61        5
00236 #define    ISC60        4
00237 #define    ISC51        3
00238 #define    ISC50        2
00239 #define    ISC41        1
00240 #define    ISC40        0
00241  
00242 /* External Interrupt MaSK register */
00243 #define    INT7         7
00244 #define    INT6         6   
00245 #define    INT5         5
00246 #define    INT4         4
00247 #define    INT3         3
00248 #define    INT2         2
00249 #define    INT1         1
00250 #define    INT0         0
00251  
00252 /* Èxternal Interrupt Flag Register */
00253 #define    INTF7        7
00254 #define    INTF6        6
00255 #define    INTF5        5
00256 #define    INTF4        4
00257  
00258 /* Timer/Counter Interrupt MaSK register */ 
00259 #define    OCIE2        7
00260 #define    TOIE2        6
00261 #define    TICIE1       5
00262 #define    OCIE1A       4
00263 #define    OCIE1B       3
00264 #define    TOIE1        2
00265 #define    OCIE0        1
00266 #define    TOIE0        0
00267  
00268 /* Timer/Counter Interrupt Flag Register */
00269 #define    OCF2         7
00270 #define    TOV2         6
00271 #define    ICF1         5
00272 #define    OCF1A        4
00273 #define    OCF1B        3
00274 #define    TOV1         2
00275 #define    OCF0         1
00276 #define    TOV0         0      
00277  
00278 /* MCU general Control Register */
00279 #define    SRE          7
00280 #define    SRW          6
00281 #define    SE           5
00282 #define    SM1          4
00283 #define    SM0          3
00284  
00285 /* MCU Status Register */ 
00286 #define    EXTRF        1
00287 #define    PORF         0
00288  
00289 /* Timer/Counter 0 Control Register */
00290 #define    PWM0         6
00291 #define    COM01        5
00292 #define    COM00        4
00293 #define    CTC0         3
00294 #define    CS02         2
00295 #define    CS01         1
00296 #define    CS00         0
00297  
00298 /* Timer/Counter 0 Asynchronous Control & Status Register */ 
00299 #define    AS0          3
00300 #define    TCN0UB       2
00301 #define    OCR0UB       1
00302 #define    TCR0UB       0 
00303  
00304 /* Timer/Counter 1 Control Register */ 
00305 #define    COM1A1       7
00306 #define    COM1A0       6
00307 #define    COM1B1       5
00308 #define    COM1B0       4
00309 #define    PWM11        1
00310 #define    PWM10        0
00311  
00312 /* Timer/Counter 1 Control and Status Register */
00313 #define    ICNC1        7
00314 #define    ICES1        6
00315 #define    CTC1         3
00316 #define    CS12         2
00317 #define    CS11         1
00318 #define    CS10         0
00319  
00320 /* Timer/Counter 2 Control register */ 
00321 #define    PWM2         6
00322 #define    COM21        5
00323 #define    COM20        4
00324 #define    CTC2         3
00325 #define    CS22         2
00326 #define    CS21         1
00327 #define    CS20         0
00328  
00329 /* Watchdog Timer Control Register */ 
00330 #define    WDTOE        4
00331 #define    WDE          3
00332 #define    WDP2         2
00333 #define    WDP1         1
00334 #define    WDP0         0
00335   
00336 /* EEPROM Control Register */
00337 #define    EERIE        3
00338 #define    EEMWE        2
00339 #define    EEWE         1
00340 #define    EERE         0
00341  
00342 /* Data Register, Port A */
00343 #define    PA7          7
00344 #define    PA6          6
00345 #define    PA5          5
00346 #define    PA4          4
00347 #define    PA3          3
00348 #define    PA2          2
00349 #define    PA1          1
00350 #define    PA0          0
00351  
00352 /* Data Direction Register, Port A */ 
00353 #define    DDA7         7
00354 #define    DDA6         6
00355 #define    DDA5         5
00356 #define    DDA4         4
00357 #define    DDA3         3
00358 #define    DDA2         2
00359 #define    DDA1         1
00360 #define    DDA0         0
00361    
00362 /* Input Pins, Port A */ 
00363 #define    PINA7        7
00364 #define    PINA6        6
00365 #define    PINA5        5
00366 #define    PINA4        4
00367 #define    PINA3        3
00368 #define    PINA2        2
00369 #define    PINA1        1
00370 #define    PINA0        0
00371  
00372 /* Data Register, Port B */ 
00373 #define    PB7          7
00374 #define    PB6          6
00375 #define    PB5          5
00376 #define    PB4          4
00377 #define    PB3          3
00378 #define    PB2          2
00379 #define    PB1          1
00380 #define    PB0          0
00381  
00382 /* Data Direction Register, Port B */
00383 #define    DDB7         7
00384 #define    DDB6         6
00385 #define    DDB5         5
00386 #define    DDB4         4
00387 #define    DDB3         3
00388 #define    DDB2         2
00389 #define    DDB1         1
00390 #define    DDB0         0
00391                       
00392 /* Input Pins, Port B */
00393 #define    PINB7        7
00394 #define    PINB6        6
00395 #define    PINB5        5
00396 #define    PINB4        4
00397 #define    PINB3        3
00398 #define    PINB2        2
00399 #define    PINB1        1
00400 #define    PINB0        0
00401  
00402 /* Data Register, Port C */
00403 #define    PC7          7
00404 #define    PC6          6
00405 #define    PC5          5
00406 #define    PC4          4
00407 #define    PC3          3
00408 #define    PC2          2
00409 #define    PC1          1
00410 #define    PC0          0
00411  
00412 /* Data Register, Port D */
00413 #define    PD7          7
00414 #define    PD6          6
00415 #define    PD5          5
00416 #define    PD4          4
00417 #define    PD3          3
00418 #define    PD2          2
00419 #define    PD1          1
00420 #define    PD0          0
00421                                           
00422 /* Data Direction Register, Port D */
00423 #define    DDD7         7
00424 #define    DDD6         6
00425 #define    DDD5         5
00426 #define    DDD4         4
00427 #define    DDD3         3
00428 #define    DDD2         2
00429 #define    DDD1         1
00430 #define    DDD0         0
00431  
00432 /* Input Pins, Port D */
00433 #define    PIND7        7
00434 #define    PIND6        6
00435 #define    PIND5        5
00436 #define    PIND4        4
00437 #define    PIND3        3
00438 #define    PIND2        2
00439 #define    PIND1        1
00440 #define    PIND0        0
00441  
00442 /* Data Register, Port E */
00443 #define    PE7          7
00444 #define    PE6          6
00445 #define    PE5          5
00446 #define    PE4          4
00447 #define    PE3          3
00448 #define    PE2          2
00449 #define    PE1          1
00450 #define    PE0          0
00451  
00452 /* Data Direction Register, Port E */
00453 #define    DDE7         7
00454 #define    DDE6         6
00455 #define    DDE5         5
00456 #define    DDE4         4
00457 #define    DDE3         3
00458 #define    DDE2         2
00459 #define    DDE1         1
00460 #define    DDE0         0
00461  
00462 /* Input Pins, Port E */
00463 #define    PINE7        7
00464 #define    PINE6        6
00465 #define    PINE5        5
00466 #define    PINE4        4
00467 #define    PINE3        3
00468 #define    PINE2        2
00469 #define    PINE1        1
00470 #define    PINE0        0
00471  
00472 /* Input Pins, Port F */
00473 #define    PINF7        7
00474 #define    PINF6        6
00475 #define    PINF5        5
00476 #define    PINF4        4
00477 #define    PINF3        3
00478 #define    PINF2        2
00479 #define    PINF1        1
00480 #define    PINF0        0
00481  
00482 /* SPI Status Register */ 
00483 #define    SPIF         7
00484 #define    WCOL         6
00485  
00486 /* SPI Control Register */
00487 #define    SPIE         7
00488 #define    SPE          6
00489 #define    DORD         5
00490 #define    MSTR         4
00491 #define    CPOL         3
00492 #define    CPHA         2
00493 #define    SPR1         1
00494 #define    SPR0         0
00495   
00496 /* UART Status Register */
00497 #define    RXC          7
00498 #define    TXC          6
00499 #define    UDRE         5
00500 #define    FE           4
00501 #define    OVR          3    /*This definition differs from the databook    */
00502                         /*definition to avoid problems with the OR instruction */
00503  
00504 /* UART Control Register */
00505 #define    RXCIE        7
00506 #define    TXCIE        6
00507 #define    UDRIE        5
00508 #define    RXEN         4
00509 #define    TXEN         3
00510 #define    CHR9         2
00511 #define    RXB8         1
00512 #define    TXB8         0
00513  
00514 /* Analog Comparator Control and Status Register */
00515 #define    ACD          7
00516 #define    ACO          5
00517 #define    ACI          4
00518 #define    ACIE         3
00519 #define    ACIC         2
00520 #define    ACIS1        1
00521 #define    ACIS0        0
00522  
00523 /* ADC Control and status register */
00524 #define    ADEN         7
00525 #define    ADSC         6
00526 #define    ADFR         5
00527 #define    ADIF         4
00528 #define    ADIE         3
00529 #define    ADPS2        2
00530 #define    ADPS1        1
00531 #define    ADPS0        0
00532  
00533 /* ADC Multiplexer select */
00534 #define    MUX2         2
00535 #define    MUX1         1
00536 #define    MUX0         0
00537  
00538 /* Pointer definition */
00539 #define    XL       r26
00540 #define    XH       r27
00541 #define    YL       r28
00542 #define    YH       r29
00543 #define    ZL       r30
00544 #define    ZH       r31
00545 
00546 /* Constants */
00547 #define    RAMEND   0x0FFF     /*Last On-Chip SRAM Location*/
00548 #define    XRAMEND  0xFFFF
00549 #define    E2END    0x0FFF
00550 #define    FLASHEND 0x1FFFF
00551  
00552 #endif

Generated at Fri Jul 19 14:55:41 2002 for avrgcc by doxygen1.2.8.1 written by Dimitri van Heesch, © 1997-2001