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00018 #include <avr/io.h>
00019 #include <avr/signal.h>
00020 #include <avr/interrupt.h>
00021
00022 #include "global.h"
00023 #include "sramsw.h"
00024
00025
00026
00027
00028 void sramswInit(void)
00029 {
00030
00031 outb(SRAM_ADL, 0xFF);
00032 outb(SRAM_AH, 0x00);
00033
00034 outb(SRAM_ADL_DDR, 0x00);
00035 outb(SRAM_AH_DDR, 0xFF);
00036
00037 sbi(SRAM_CTRL, SRAM_WR);
00038 sbi(SRAM_CTRL, SRAM_RD);
00039 cbi(SRAM_CTRL, SRAM_ALE);
00040
00041 sbi(SRAM_CTRL_DDR, SRAM_WR);
00042 sbi(SRAM_CTRL_DDR, SRAM_RD);
00043 sbi(SRAM_CTRL_DDR, SRAM_ALE);
00044
00045 outb(SRAM_PAGE_DDR, inb(SRAM_PAGE_DDR) | SRAM_PAGE_MASK );
00046
00047 sramswSetPage(0);
00048 }
00049
00050 void sramswOff(void)
00051 {
00052 }
00053
00054 void sramswWrite(u32 addr, u08 data)
00055 {
00056
00057 sramswSetPage( (addr & 0x00FF0000)>>16 );
00058
00059 outb(SRAM_AH, (addr & 0x0000FF00)>>8 );
00060
00061 outb(SRAM_ADL, addr & 0x000000FF);
00062
00063 outb(SRAM_ADL_DDR, 0xFF);
00064
00065 sbi(SRAM_CTRL, SRAM_ALE);
00066 asm volatile ("nop");
00067 cbi(SRAM_CTRL, SRAM_ALE);
00068
00069
00070 outb(SRAM_ADL, data);
00071
00072 cbi(SRAM_CTRL, SRAM_WR);
00073 asm volatile ("nop");
00074 sbi(SRAM_CTRL, SRAM_WR);
00075 }
00076
00077 u08 sramswRead(u32 addr)
00078 {
00079 u08 data;
00080
00081
00082 sramswSetPage( (addr & 0x00FF0000)>>16 );
00083
00084 outb(SRAM_AH, (addr & 0x0000FF00)>>8 );
00085
00086 outb(SRAM_ADL, addr & 0x000000FF);
00087
00088 outb(SRAM_ADL_DDR, 0xFF);
00089
00090 sbi(SRAM_CTRL, SRAM_ALE);
00091 asm volatile ("nop");
00092 cbi(SRAM_CTRL, SRAM_ALE);
00093
00094
00095 outb(SRAM_ADL_DDR, 0x00);
00096
00097 outb(SRAM_ADL, 0x00);
00098
00099 cbi(SRAM_CTRL, SRAM_RD);
00100
00101 asm volatile ("nop");
00102 data = inb(SRAM_ADL_IN);
00103
00104 sbi(SRAM_CTRL, SRAM_RD);
00105
00106 outb(SRAM_ADL_DDR, 0xFF);
00107
00108 return data;
00109 }
00110
00111 void sramswSetPage(u08 page)
00112 {
00113 outb(SRAM_PAGE, (page & SRAM_PAGE_MASK));
00114 }